Advanced Process DesignWith a strong partnership with the world’s most leading foundry, Alchip is always the first in the industry to design with the industry’s most leading edge processes.
Alchip’s various unique design solutions for double pattern technology, coloring and cut metal, which are essential for processes beyond 16nm, are in place to enable our customer products to be competitive in their markets.As of October 2019, we have more tapeouts and mass production results than any other pure play ASIC competitors in the leading-edge FinFET process of 16nm and beyond. We are developing quite a few 7nm products with our customers now, which include multiple challenging 2.5D CoWoS. In parallel, we are preparing to engage projects based on our N6 and N5P technology platform. Our N5P platform is being developed to enable our customer tape-out in Q4 2020.2. 低功耗
Power Efficient HPC Methodology Cuts Power by 30%Alchip’s best-in-class advanced power management techniques address both static and dynamic power management requirements. A unique clocking architecture and timing methodology achieves up to 30% dynamic power savings by effectively reducing overall capacitance. And gated-clock designs and multi-supply voltage portioning further reduces dynamic power usage.
Alchip’s complete design methodology supports emerging ultra-low power process nodes and offers the flexibility to re-characterize IP for ultra-low voltage usage.
We have close partnerships with all major EDA vendors and incorporate the features of the most advanced EDA tools into our low-power design methodology.
Provide Cutting-edge SoC PackageAlchip offers a wide range of package solutions from low-end QFN / QFP to high-end packages such as FCBGA (Flip Chip), MCM (Multi Chip Module), WLCSP (Wafer Level CSP), and 2.5D CoWoS.
In particular, our Cu wire bonding with high-power, high-power flip-chip and micro-bump chip-on-chip technology using a substrate with a body size exceeding 85×85 mm2 and 14 layers remains a pioneer in the world today. We have sufficient mass production records to demonstrate our manufacturing capability in handling our customer products in mass production.
Package / Substrate DesignWith an in-house design system, it makes us possible to design an optimal substrate through close cooperation between the SoC designer and the substrate designer. It provides the best solution to balance between performance, cost and schedule.
LSI TestTo become a trusted silicon partner for customers, we believe that it is not only simply providing superior manufacturing capabilities, but also ensuring superior quality through testing.
Our test support covers all kinds of tests from low price to high price SoCs.
Optimized according to the characteristics evaluation and product specifications, we can help you achieve efficient evaluation in a short period of time.
Furthermore, we offer multi-site and concurrent tests to reduce costs in the mass production stage. In addition, based on thorough characterization, we can reduce redundant test items in wafer and package tests, minimizes test time without compromising measurement quality, and contributes to customer cost reduction.
Alchip’s test program and jig development flow is divided into five steps to ensure that our customers receive the highest quality products.
Select the best testerTest program development results with ADVANTEST (including former Verigy), TERADYNE and LTX-Credence.
We own a tester (V93K) in a test house which can be used in the design stage.
Design and manufacture of test jigWe have bounty experience in designing and manufacturing jigs such as probe cards, load boards, sockets and change kits.
Pattern conversionWe support various formats such as STIL, WGL and VCD, and can quickly convert over 500 pattern files.
Test program developmentIn-house test programs are developed based on development results from basic logic tests, such as SCAN, Memory BIST, JTAG, etc., to high-speed interface tests, such as DDR, PCIe, USB, SATA, LVDS, and analog tests, such as ADC, DAC, RF, etc.
In addition, since detailed simulation is performed when designing jigs, debugging in a short period of time is made possible.
CharacterizationFinally, we will evaluate characteristics such as voltage and timing margin.